1. Field of the Invention
The present invention relates to a semiconductor device having a multi-layered wiring arrangement produced by using a damascene process, and a production method for manufacturing such a semiconductor device.
2. Description of the Related Art
In a representative process of producing a plurality of semiconductor devices, for example, a silicon wafer is prepared, and a surface of the silicon wafer is sectioned into a plurality of semiconductor chip areas by forming grid-like fine grooves (i.e. scribe lines) in the silicon wafer. Then, the silicon wafer is processed by various well-known methods such that each of the semiconductor chip areas is produced as a semiconductor device, and an insulating layer is formed as an underlayer on the semiconductor devices produced in the silicon wafer. A plurality of metal plugs are formed in an area of the insulating underlayer, which corresponds to each of the semiconductor devices, with the metal plugs being electrically connected to a corresponding semiconductor device.
Subsequently, a multi-layered wiring arrangement is formed on the insulating underlayer of the silicon wafer, using various processes, for example, a chemical vapor deposition (CVD) process, a photolithography process, an etching process, a sputtering process, an electroplating process, and so on. The multi-layered wiring arrangement includes a lowermost insulating layer structure formed on the insulating underlayer of the silicon wafer and having a plurality of metal wiring patterns formed therein, an uppermost insulating layer structure having a plurality of metal wiring patterns formed therein, and at least one intermediate insulating layer structure or insulating interlayer structure provided between the lowermost and uppermost insulating layer structures and having a plurality of metal wiring patterns. Conventionally, each of the lowermost and uppermost insulating layer structures is formed as a silicon dioxide layer by the CVD process, and the insulating interlayer structure is also formed as a silicon dioxide layer by the CVD process.
Each of the metal wiring patterns included in the lowermost insulating layer structure is electrically connected to the metal plugs provided for a corresponding semiconductor device. Also, each of the metal wiring patterns included in the insulating interlayer structure is electrically connected to a corresponding metal wiring pattern of the lowermost insulating layer structure through the intermediary of via-plugs formed in the insulating interlayer structure. Further, each of the metal wiring patterns included in the uppermost insulating layer structure is electrically connected to a corresponding metal wiring pattern of the insulating interlayer structure through the intermediary of via-plugs formed in the uppermost insulating layer structure.
With the recent advance of miniaturization of semiconductor devices, a signal-transmission path included in each metal wiring pattern becomes narrower. Of course, the narrower the signal-transmission path, the larger resistance of the signal-transmission path, resulting in delay of signal transmission in the signal-transmission path. Conventionally, in general, although the metal wiring patterns are formed of aluminum, there is a recent trend toward use of copper, exhibiting a smaller specific resistance than that of aluminum, for the metal wiring pattern, whereby the signal transmission can be facilitated in the signal-transmission paths of the metal wiring pattern.
Also, the signal-transmission paths included in each metal wiring pattern become closer to each other for the miniaturization of semiconductor devices, and thus a parasitic capacitance is produced between adjacent signal-transmission paths because the silicon dioxide layer serves as a dielectric therebetween. Of course, the production of the parasitic capacitance results in delay of signal transmission in the signal-transmission paths. In short, the miniaturization of the semiconductor devices has advanced to a degree in which a magnitude of a dielectric constant of the silicon dioxide layer cannot be neglected.
Thus, in the production of the semiconductor devices, it has been proposed that an insulating layer, composed of a low-k material having a smaller dielectric constant than that of silicon dioxide, be substituted for the silicon dioxide insulating layer, to thereby suppress the production of the parasitic capacitance. Note, for the low-k material, SiOCH is representatively used.
In general, since it is difficult to minutely process a copper layer by using a dry etching process to thereby produce a copper wiring pattern, a damascene process is used for the production of the minute copper wiring pattern, as disclosed in, for example, JP-A-2002-026121 and JP-A-2003-017561.
In the production of the aforesaid multi-layered wiring arrangement by using the damascene process, a SiOCH insulating layer is exposed to an oxidizing atmosphere, and thus it is difficult to completely substitute the SiOCH insulating layer for the silicon dioxide insulating layer, because the SiOCH insulating layer exhibits an oxidation resistance property which is inferior to that of the silicon dioxide insulating layer. Namely, the SiOCH insulating layer is liable to be oxidized due to a carbon component (C) contained therein.
Accordingly, in the damascene process, after the SiOCH insulating layer is formed, a thin silicon dioxide insulating layer is further formed as a protective layer over the SiOCH insulating layer. However, an adhesion strength is relatively low in an interface between the SiOCH insulating layer and the thin silicon dioxide insulating layer, due to existence of Si—CH3 bonds on the interfacial surface of the SiOCH insulating layer, and thus both the layers are liable to be separated from each other. Further, when the SiOCH insulating layer and the silicon dioxide insulating layer are formed by a plasma chemical vapor deposition (CVD) process, a tensile stress is produced in the SiOCH insulating layer, whereas a compression stress is produced in the silicon dioxide insulating layer. Thus, both the layers are further liable to be separated from each other.
In order to improve the oxidation resistance property of the SiOCH insulating layer and the adhesion property in the interface between SiOCH insulating layer and the thin silicon dioxide insulating layer, it has been proposed that the surface of the SiOCH insulating layer be subjected to a plasma treatment using a plasma gas containing oxygen (O), to thereby reform and modify the surface of the SiOCH insulating layer before the formation of the thin silicon dioxide insulating layer, as disclosed in the aforesaid JP-A-2002-026121. However, this plasma treatment is unsatisfactory in that it is difficult to reform and modify only a surface section of the SiOCH insulating layer. Namely, when the SiOCH insulating layer is treated with the plasma gas containing oxygen (O), it can be wholly reformed and modified, due to the poor oxidation resistance property of the SiOCH insulating layer. In other words, it is very difficult to control the plasma treatment such that only the surface section of the SiOCH insulating layer is reformed and modified.
On the other hand, the aforesaid JP-A-2003-017561 discloses a plasma treatment using a reducing gas for reforming and modifying the surface section of the SiOCH insulating layer. When a gas containing nitrogen (N), such as an N2 gas, an NH3 gas or the like, is used as the reducing gas, the SiOCH insulating layer is nitrided, resulting in a rise in the dielectric constant of the SiOCH insulating layer.
Also, when a hydrogen (H2) gas is used as the reducing gas, it is possible to increase desirable Si—H bonds in the surface section of the SiOCH insulating layer. Nevertheless, the hydrogen atoms (H) are liable to be separated from the Si—H bonds in a post-treatment, because the Si—H bonds are thermally unstable. Further, since the hydrogen atoms (H) can be easily diffused in the SiOCH insulating layer, it is very difficult to reform and modify only the surface section of the SiOCH insulating layer. In addition, since the methyl radicals (CH3—) are decreased from the reformed and modified surface section of the SiOCH insulating layer, it exhibits a high moisture-absorption characteristic. Of course, it is undesirable that the reformed and modified surface section of the SiOCH insulating layer contains moisture.